类 型
6 篇文献
 
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization  
As technology scales down to nanometer regime the process variations have profound effect on circuit characteristics. Meeting timing and power constraints under such process variations in nano-CMOS ci......
VLSI Design  2011
0次引用 0 0
Adaptive test directions  
This paper describes the development of adaptive test in response to the ever growing need to dynamically and cost effectively tailor IC testing to discriminately manage manufacturing process variatio......
European Test Symposium  2010
2次引用 0 0
Adaptive Testing: Dealing with Process Variability  
This article describes the development of adaptive testing in response to the ever-growing need to dynamically and cost-effectively tailor IC testing to discriminately manage manufacturing process var......
IEEE Design and Test of Computers  2011
0次引用 0 0
An architecture-level approach for mitigating the impact of process variations on extensible processors  
In this paper, we present an architecture-level approach to mitigate the impact of process variations on extended instruction set architectures (ISAs). The proposed architecture adds one extra cycle t......
Design, Automation, and Test in Europe  2012
0次引用 0 0
Timing Analysis Techniques Review for sub-30 nm Circuit Designs  
Abstract—With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost is......
0次引用 0 0
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization  
Abstract: As the CMOS technology scales down to nanometer regime the process variations have profound effect on circuit attributes. Meeting timing and power constraints under such process variations i......
Journal of Low Power Electronics  2011
0次引用 0 0

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