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13 篇文献
 
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization  
As technology scales down to nanometer regime the process variations have profound effect on circuit characteristics. Meeting timing and power constraints under such process variations in nano-CMOS ci......
VLSI Design  2011
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Investigation of Latch based Design (December 2009)  
Abstract—Conventionally flip-flop based designs are used in digital circuits, because of the ease of timing analysis and verification. However using latches instead of flip flops selectively offers se......
0次引用 0 0
A runtime adaptive controller for supporting hardware components with variable latency  
Nowadays, the design of hardware cores has to necessarily deal with unpredictable components, due to process variation or to the interaction with external modules (e.g., memories, sensors, IP cores). ......
Adaptive Hardware and Systems  2011
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operation scheduling considering time borrowing for high-performance latch-based circuits  
Recently, latch-based design has attracted attention due to its several merits. Time borrowing is one feature of latches, where a slower functional unit can borrow timing slacks from a faster function......
Annual IEEE Northeast Workshop on Circuits and Systems  2011
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Statistical High-Level Synthesis under Process Variability  
CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys......
IEEE Design and Test of Computers  2009
6次引用 0 0
Ordered coloring-based resource binding for datapaths with improved skew-adjustability  
This paper proposes a novel high level synthesis for post-silicon skew adjustable datapaths. Our objective in high level synthesis is to maximize the "skew adjustability", i.e. the probability of the ......
ACM Great Lakes Symposium on VLSI  2011
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Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis  
Flip-flop (FF)/latch-based design has advantages on such as area and power compared to single register-type design (only FFs or latches). Considering FF/latch-based design at high-level synthesis is n......
ACM Great Lakes Symposium on VLSI  2012
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Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation  
In recent application-specific integrated circuit design, using transparent latches as storage elements has been intensively studied, since designs using latches (latch-based design) has a large poten......
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statistical timing-yield driven scheduling and fu binding in latch-based datapath synthesis  
In the presence of process variation, conventional worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. As a result, statistical static timing analysis......
Midwest Symposium on Circuits and Systems  2012
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Timing variation-aware scheduling and resource binding in high-level synthesis  
Due to technological scaling, process variations have increased significantly, resulting in large variations in the delay of the functional units. Hence, the worst-case approach is becoming increasing......
ACM Transactions on Design Automation of Electronic Systems  2011
0次引用 0 0

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