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8 篇文献
 
Test Challenges for 3D Integrated Circuits  
One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including p......
IEEE Design and Test of Computers  2009
16次引用 0 0
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs  
Core based three-dimensional(3D) integrated circuits (ICs) design is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced powe......
Annual Symposium on VLSI  2011
0次引用 0 0
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint  
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. In contrast to prior ......
IEEE International Conference on Computer-Aided Design  2009
9次引用 0 0
Clock tree synthesis with pre-bond testability for 3D stacked IC designs  
This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the ......
Design Automation Conference  2010
14次引用 0 0
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs  
Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs of......
IEEE VLSI Test Symposium  2011
12次引用 0 0
Test architecture design and optimization for three-dimensional SoCs  
Core-based system-on-chips (SoCs) fabricated on three-dimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimization techniques are e......
Design, Automation, and Test in Europe  2009
8次引用 0 0
DfT Architecture for 3D-SICs with Multiple Towers  
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-......
European Test Symposium  2011
11次引用 0 0
3DICE: 3D IC cost evaluation based on fast tier number estimation  
During the billion transistor era, 3D stacking offers an attractive solution for the difficulties resulting from large-scale design complexities. Moreover, 3D stacking can benefit performance, power, ......
International Symposium on Quality Electronic Design  2011
0次引用 0 0

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