IEEE International Symposium on Circuits and Systems  - ISCAS

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A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches  
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IEEE International Symposium on Circuits and Systems  2013
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Tsung-Heng Tsai , Bo-Han Song
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A power-efficient scan tree design by exploring the Q'-D connection  
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IEEE International Symposium on Circuits and Systems  2013
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High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit  
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IEEE International Symposium on Circuits and Systems  2013
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A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist  
Chi-Shin Chang , Hao-i Yang , Wei-Nan Liao , Yi-Wei Lin , Nan-Chun Lien , Chien-Hen Chen , Ching-Te Chuang , Wei Hwang , Shyh-Jye Jou , Ming-Hsien Tu , Huan-Shun Huang , Yong-Jyun Hu , Kan, P.-S. , Cheng-Yo Cheng , Wei-Chang Wang , Jian-Hao Wang , Kuen-Di Lee , Chia-cheng Chen , Wei-Chiang Shih
IEEE International Symposium on Circuits and Systems  2013
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主要作者
Paul E. Hasler
Georgia Institute of Technology
 
Franco Maloberti
CERN, Geneva
 
Jaime Ramirez-angulo
Mixed Signal Design Dept., Texas Instrum. Inc., Dallas, TX
 
Kari Halonen
Helsinki University of Technology
 
Randall L. Geiger
Motorola Inc.
 
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