IEEE International Symposium on Multiple-Valued Logic  - ISMVL

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A New Approach to Use Partial Results During Image Computation in BDD Based Symbolic Model Checking  
Christian Appold
IEEE International Symposium on Multiple-Valued Logic  2014
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Implication Graph Compression inside the SMT Solver iSAT3  
Karsten Scheibler , Bernd Becker
IEEE International Symposium on Multiple-Valued Logic  2014
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Synthesis of Distributed Synchronous Specifications to SysteMoC  
Mohamed Ammar Ben Khadra , Yu Bai , Klaus Schneider
IEEE International Symposium on Multiple-Valued Logic  2014
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Verifikation Rekonfigurierbarer Scan-Netze  
Rafal Baranowski , Michael A. Kochte , Hans-Joachim Wunderlich
IEEE International Symposium on Multiple-Valued Logic  2014
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Dynamically Reconfigurable Constant Multiplication on FPGAs  
Konrad Möller , Martin Kumm , Björn Barschtipan , Peter Zipf
IEEE International Symposium on Multiple-Valued Logic  2014
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主要作者
Rolf Drechsler
University of Bremen
 
Tsutomu Sasao
Kyushu Institute of Technology
 
Takahiro Hanyu
Tohaku University
 
Marek Perkowski
Portland State University
 
Michitaka Kameyama
Tohoku University
 
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