Static Timing Analysis
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Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (Placement (EDA)|placement and Routing (EDA)|routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous SPICE|circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The speedup appears due to the use of...
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