Logic Synthesis
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In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of Hardware Description Language|HDLs, including VHDL and Verilog. Some tools can generate bitstreams for programmable logic devices such as programmable array logic|PALs or Field-programmable gate array|FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.
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