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Perceptron-based Coherence Predictors   
摘  要:   Coherence misses in shared-memory multiprocessors ac- count for a substantial fraction of execution time in many important workloads. Just as branch predictors reduce the performance impact of branches, coherence predictors can reduce the performance impact of coherence misses. Two-level pattern-based coherence predictors have offere d a general prediction method to trigger appropriate coher- ence actions. This paper presents the design and evalua- tion of a perceptron-based coherence predictor that extend s a conventional directory-based write-invalidate protoco l to predict when to push updates to remote nodes. When pre- dicted correctly, the update eliminates a coherence miss on the remote node. We also present a simple mechanism for predicting to which nodes we should push updates. We evaluate our perceptron-based update predictor on a variety of SPLASH-2 and PARSEC benchmarks. Simulation indicates that the update predictor eliminates an average o f 30% of coherence misses. Our simple consumer prediction mechanism sent very few useless updates - on average 87% of updates were consumed (eliminated misses).
发  表:   2008

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