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Yibo Chen 的引文(44) 排序方式:
A power-efficient reconfigurable architecture using PCM configuration technology  
Promising advantages offered by resistive NonVolatile Memories (NVMs) have brought great attention to replace existing volatile memory technologies. While NVMs were primarily studied to be used in the......
Automation \and Test in Europe Proceedings of the Conference on Design  2014
0次引用 0 0
An accurate semi-analytical framework for full-chip TSV-induced stress modeling  
TSV-induced stress is an important issue in 3D IC design since it leads to serious reliability problems and influences device performance. Existing finite element method can provide accurate analysis ......
Design Automation Conference  2013
0次引用 0 0
Thermomechanical stress-aware management for 3D IC designs  
The thermomechanical stress has been considered as one of the most challenging problems in three-dimensional integration circuits (3D ICs), due to the thermal expansion coefficient mismatch between th......
Design, Automation, and Test in Europe  2013
0次引用 0 0
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis  
Flip-flop (FF)/latch-based design has advantages on such as area and power compared to single register-type design (only FFs or latches). Considering FF/latch-based design at high-level synthesis is n......
ACM Great Lakes Symposium on VLSI  2012
0次引用 0 0
statistical timing-yield driven scheduling and fu binding in latch-based datapath synthesis  
In the presence of process variation, conventional worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. As a result, statistical static timing analysis......
Midwest Symposium on Circuits and Systems  2012
0次引用 0 0
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)  
In this study, we explore the use of Resistive RAMs (RRAMs) as candidates for programmable interconnects in FPGAs. An RRAM cell can be programmed between high resistance state and low resistance state......
Symposium on Field Programmable Gate Arrays  2012
1次引用 0 0
An architecture-level approach for mitigating the impact of process variations on extensible processors  
In this paper, we present an architecture-level approach to mitigate the impact of process variations on extended instruction set architectures (ISAs). The proposed architecture adds one extra cycle t......
Design, Automation, and Test in Europe  2012
0次引用 0 0
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs  
Core based three-dimensional(3D) integrated circuits (ICs) design is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced powe......
Annual Symposium on VLSI  2011
0次引用 0 0
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs  
Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs of......
IEEE VLSI Test Symposium  2011
12次引用 0 0
DfT Architecture for 3D-SICs with Multiple Towers  
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-......
European Test Symposium  2011
11次引用 0 0

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