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Yibo Chen 的论文(29) 排序方式:
Tolerating process variations in high-level synthesis using transparent latches  
Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced control steps and redu......
Asia and South Pacific Design Automation Conference  2009
13次引用 0 0
Test-access mechanism optimization for core-based three-dimensional SOCs  
Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Such a modular testing app......
International Conference on Computer Design  2008
8次引用 0 0
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement  
In recent years, many systems have employed NAND flash memory as storage devices because of its advantages of higher performance (compared to the traditional hard disk drive), high-density, random-acc......
International Symposium on High-Performance Computer Architecture  2010
8次引用 0 0
Statistical High-Level Synthesis under Process Variability  
CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys......
IEEE Design and Test of Computers  2009
6次引用 0 0
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs  
The three-dimensional integrated circuits (3D ICs) offer performance advantages thanks to the increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionall......
International Symposium on Low Power Electronics and Design  2011
2次引用 0 0
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory  
Memories play a key role in FGPAs in the forms of both programming bits and embedded memory blocks. FPGAs using non-volatile memories have been the focus of attention with zero boot-up delay, real-tim......
International Symposium on Low Power Electronics and Design  2010
2次引用 0 0
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis  
Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, sm......
IEEE International Conference on Computer-Aided Design  2010
2次引用 0 0
Variation-Aware Task and Communication Mapping for MPSoC Architecture  
As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicrometer designs. As a result, a paradigm shift from deterministic to statistic......
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems  2011
1次引用 0 0
Test-access mechanism optimization for core-based three-dimensional SOCs  
Microelectronics Journal  2010
1次引用 0 0
Parametric yield driven resource binding in behavioral synthesis with multi- V th /V dd library  
The ever-increasing chip power dissipation in SoCs has imposed great challenges on today's circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is a......
 2010
1次引用 0 0

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